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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 21. Enable (EnableReg) Register (Address: 0x10)
BIT
0
NAME
enable
FUNCTION
SPI equivalent of the ENABLE pin, which should be kept low (0) if the external ENABLE pin is used. The
external ENABLE pin should also be kept low (0) if the enable bit is used.
Table 22. Data Input (DataReg) Register (Address: 0x11)
BIT
0
NAME
datain
FUNCTION
SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It should
be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept low (0) if the
datain bit is used.
Table 23. Statu s (Status) Register (Address: 0x12)
BIT
7:0
NAME
status[7:0]
FUNCTION
Read-only status register, selected through tmux[2:0] (register 0x04 IOConf0)
Table 24. Status Bus Signals
tmux[2:0]
0
1
2
3
4
5
6
7
status[7]
—
—
—
—
—
integ[3]
frac[7]
—
status[6]
—
—
—
frac_fxdb
—
integ[2]
frac[6]
—
status[5]
—
—
—
—
notover
integ[1]
frac[5]
—
status[4]
—
—
—
cap[4]
capfxd[4]
integ[0]
frac[4]
—
status[3]
ckout
—
enable
cap[3]
capfxd[3]
frac[11]
frac[3]
—
status[2]
ckd16
—
—
cap[2]
capfxd[2]
frac[10]
frac[2]
—
status[1]
ckd4
—
—
cap[1]
capfxd[1]
frac[9]
frac[1]
lockdet
status[0]
nock
—
—
cap[0]
capfxd[0]
frac[8]
frac[0]
xmit_en
—
nock
Reserved signals
No-clock flag (1) if crystal oscillator is dis-
frac_fxdb
Fractional-N mode (1) or ASK fixed-N mode
(0)
abled, and (0) ic clock activity is observed
capfxd[4:0] Emulation mode variable capacitor setting
ckd4
ckd16
ckout
enable
cap[4:0]
Crystal clock signal divided by 4
Crystal clock signal divided by 16
Clock output signal, according to pro-
grammed dividers (ckdiv[2:0])
Internal enable signal (OR function of the
ENABLE pin and enable bit)
SPI mode capacitor setting
notover
integ[3:0]
frac[11:0]
xmit_en
lockdet
ASK digital shaping flag (1) when PA power
value is different than 0
Fractional-N 4-bit integer value
Fractional-N 12-bit fractional value
Transmitter PA enable flag
PLL lock-detect flag
Maxim Integrated
25
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